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WSE128K16-XXX
128KX16 SRAM/EEPROM MODULE
FEATURES
s Access Times of 35ns (SRAM) and 150ns (EEPROM) s Access Times of 45ns (SRAM) and 120ns (EEPROM) s Access Times of 70ns (SRAM) and 300ns (EEPROM) s Packaging * 66 pin, PGA Type, 1.075" square HIP, Hermetic Ceramic HIP (H1) (Package 400) * 68 lead, Hermetic CQFP (G2T), 22mm (0.880") square (Package 509). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2) s 128Kx16 SRAM s 128Kx16 EEPROM s Organized as 128Kx16 of SRAM and 128Kx16 of EEPROM Memory with separate Data Buses s Both blocks of memory are User Configurable as 256Kx8 s Low Power CMOS s Commercial, Industrial and Military Temperature Ranges
PRELIMINARY*
s TTL Compatible Inputs and Outputs s Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation s Weight - 13 grams typical
EEPROM MEMORY FEATURES
s Write Endurance 10,000 Cycles s Data Retention at 25C, 10 Years s Low Power CMOS Operation s Automatic Page Write Operation s Page Write Cycle Time 10ms Max. s Data Polling for End of Write Detection s Hardware and Software Data Protection s TTL Compatible Inputs and Outputs
* This data sheet describes a product under development, not fully characterized, and is subject to change without notice.
FIG.1
1 SD8 SD9 SD10 A13 A14 A15 A16 NC SD0 SD1 SD2 11
PIN CONFIGURATION FOR WSE128K16-XH1X PIN DESCRIPTION TOP VIEW
12 SWE2 SCS2 GND SD11 A10 A11 A12 VCC SCS1 NC SD3 22 33 23 SD15 SD14 SD13 SD12 OE NC SWE1 SD7 SD6 SD5 SD4 ED8 ED9 ED10 A6 A7 NC A8 A9 ED0 ED1 ED2 44 34 VCC ECS2 EWE2 ED11 A3 A4 A5 EWE1 ECS1 GND ED3 55 45 ED15 ED14 ED13 ED12 A0 A1 A2 ED7 ED6 ED5 ED4 66
8 8 8 8
ED0-15
56
EEPROM Data Inputs/Outputs SRAM Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected EEPROM Write Enable EEPROM Chip Select
SD0-15 A0-16 SWE1-2 SCS1-2 OE VCC GND NC EWE1-2 ECS1-2
BLOCK DIAGRAM
S W E1 S CS1 OE A0-16 128K x 8 SRAM 128K x 8 SRAM 128K x 8 EEPROM 128K x 8 EEPROM S W E2 S CS2 E W E1 E CS1 E W E2 E CS2
SD0-7
SD8-15
ED0-7
ED8-15
May 2001, Rev. 4
1
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSE128K16-XXX
FIG. 2
PIN CONFIGURATION FOR WSE128K16-XG2TX TOP VIEW
NC A0 A1 A2 A3 A4 A5 ECS1 GND ECS2 SWE1 A6 A7 A8 A9 A10 VCC
PIN DESCRIPTION
ED0-15 SD0-15
ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 GND ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15
EEPROM Data Inputs/Outputs SRAM Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected EEPROM Write Enable EEPROM Chip Select
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 GND SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
SCS1 OE SCS2 NC
SWE2 EWE1 EWE2 A11 A12 A13 A14 A15 VCC A16
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
NC NC NC
A0-16 SWE1-2 SCS1-2 OE
0.940"
VCC
The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.
GND NC EWE1-2 ECS1-2
BLOCK DIAGRAM
S W E1 S CS1 OE A0-16 128K x 8 SRAM 128K x 8 SRAM 128K x 8 EEPROM 128K x 8 EEPROM S W E2 S CS2 E W E1 E CS1 E W E2 E CS2
8
8
8
8
SD0-7
SD8-15
ED0-7
ED8-15
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
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WSE128K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC -0.5 Min -55 -65 -0.5 Max +125 +150 Vcc+0.5 150 7.0 Unit C C V C V
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Symbol VCC VIH VIL TA Min 4.5 2.0 -0.3 -55 Max 5.5 VCC + 0.3 +0.8 +125 Unit V V V C
EEPROM TRUTH TABLE CAPACITANCE (TA = +25C)
Parameter OE capacitance WE1-4 capacitance HIP (PGA) CQFP G2T CS1-4 capacitance Data I/O capacitance Address input capacitance Symbol COE CWE Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz 20 20 CCS CI/O CAD VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz 20 20 50 pF pF pF SCS H L L L OE X L H X Max 50 Unit pF pF CS H L L X X X OE X L H H X L WE X H L X H X Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out
SRAM TRUTH TABLE
SWE X H H L Mode Standby Read Read Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 16 Mode Standby Current SRAM Output Low Voltage (35 to 45ns) (70ns) (35 to 45ns) (70ns) Symbol ILI ILO ICCx16 ISB VOL VOL VOH VOH ICC1 VOL VOH1 Conditions VCC = 5.5, VIN = GND to VCC SCS = VIH, OE = VIH, VOUT = GND to VCC SCS = VIL, OE = ECS = VIH, f = 5MHz, VCC = 5.5 ECS = SCS = VIH, OE = VIH, f = 5MHz, VCC = 5.5 IOL = 8.0mA, VCC = 4.5 IOL = 2.1mA, VCC = 4.5 IOH = -4.0mA, VCC = 4.5 IOH = -1mA, VCC = 4.5 ECS = VIL, OE = SCS = VIH IOL = 2.1 mA, VCC = 4.5V IOH = 400 A, VCC = 4.5V 2.4 2.4 2.4 155 0.45 Min Max 10 10 360 31.2 0.4 0.4 Unit A A mA mA V V V V mA V V
SRAM Output High Voltage
EEPROM Operating Supply Current x 16 Mode EEPROM Output Low Voltage EEPROM Output High Voltage
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
3
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSE128K16-XXX
SRAM AC CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55C to +125C)
Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z tRC tAA tOH tACS tOE tCLZ 1 tOLZ 1 tCHZ 1 tOHZ 1 3 0 20 20 0 35 20 3 0 20 20 Symbol Min 35 35 0 45 25 3 0 25 25 -35 Max Min 45 45 3 70 35 -45 Max Min 70 70 -70 Max ns ns ns ns ns ns ns ns ns Units
1. This parameter is guaranteed by design but not tested.
SRAM AC CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55C to +125C)
Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold Time tWC tCW tAW tDW tWP tAS tAH tOW 1 tWHZ 1 tDH 0 Symbol Min 35 25 25 20 25 0 0 4 20 0 -35 Max Min 45 30 30 25 30 0 0 4 25 0 -45 Max Min 70 60 60 30 50 5 5 5 25 -70 Max ns ns ns ns ns ns ns ns ns ns Units
1. This parameter is guaranteed by design but not tested.
FIG. 3
AC TEST CIRCUIT
Current Source I OL
AC TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V
D.U.T. C eff = 50 pf
VZ
1.5V
Output Timing Reference Level
(Bipolar Supply)
I OH Current Source
NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
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WSE128K16-XXX
FIG. 4
SRAM READ CYCLE
tRC
ADDRESS
tAA
SCS
tRC
ADDRESS
tACS tCLZ
SOE
tCHZ
tAA tOH
SRAM
DATA I/O
PREVIOUS DATA VALID DATA VALID
SRAM
DATA I/O
tOE tOLZ
HIGH IMPEDANCE
tOHZ
DATA VALID
READ CYCLE 1, (SCS = OE = VIL, SWE = VIH)
READ CYCLE 2, (SWE = VIH)
FIG. 5 SRAM WRITE CYCLE SWE CONTROLLED
tWC
ADDRESS
tAW tCW
SCS
tAH
tAS
SWE
tWP tOW tWHZ tDW tDH
SRAM
DATA I/O
DATA VALID
WRITE CYCLE 1, SWE CONTROLLED
FIG. 6
SRAM WRITE CYCLE SCS CONTROLLED
tWC
ADDRESS
WS32K32-XHX
tCW tAH
tAS
SCS
tAW
tWP
SWE
tDW
SRAM DATA I/O
DATA VALID
tDH
WRITE CYCLE 2, SCS CONTROLLED
5
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSE128K16-XXX
EEPROM AC WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Write Cycle Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Write Pulse Width (EWE or ECS) Chip Select Set-up Time Address Hold Time Data Hold Time Chip Select Hold Time Data Set-up Time Output Enable Set-up Time Output Enable Hold Time Write Pulse Width High Symbol tWC tAS tWP tCS tAH tDH tCSH tDS tOES tOEH tWPH 0 150 0 100 10 0 100 10 10 50 Min Max 10 Unit ms ns ns ns ns ns ns ns ns ns ns
EEPROM WRITE
A write cycle is initiated when OE is high and a low pulse is on EWE or ECS with ECS or EWE low. The address is latched on the falling edge of ECS or EWE whichever occurs last. The data is latched by the rising edge of ECS or EWE, whichever occurs first. A byte write operation will automatically continue to completion.
WRITE CYCLE TIMING
Figures 7 and 8 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the ECS line low. Write enable consists of setting the EWE line low. The write cycle begins when the last of either ECS or EWE goes low. The EWE line transition from high to low also initiates an internal 150 sec delay timer to permit page mode operation. Each subsequent EWE transition from high to low that occurs before the completion of the 150 sec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot.
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
6
WSE128K16-XXX
FIG. 7 EEPROM WRITE WAVEFORMS EWE CONTROLLED
t WC OE t OES ADDRESS t AS ECS 1-2 t CS EWE 1-2 t WP t DS EEPROM DATA IN t WPH t DH t AH tCSH t OEH
FIG. 8
EEPROM WRITE WAVEFORMS ECS CONTROLLED
t WC OE t OES ADDRESS t AS ECS 1-2 t CS EWE 1-2 t WP t DS EEPROM DATA IN t WPH t DH t AH tCSH t OEH
7
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSE128K16-XXX
EEPROM READ
The WSE128K16-XXX EEPROM stores data at the memory location determined by the address pins. When ECS and OE are low and EWE is high, this data is present on the outputs. When ECS and OE are high, the outputs are in a high impedance state. This two line control prevents bus contention. EEPROM AC READ CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Read Cycle Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Add. Change, OE or ECS Output Enable to Output Valid Chip Select or OE to High Z Output Symbol tRC tACC tACS tOH tOE tDF 0 0 50 70 Min 120 -120 Max 120 120 0 0 55 70 Min 150 -150 Max 150 150 0 0 85 70 Min 300 -300 Max ns 300 300 ns ns ns ns ns Unit
FIG. 9
EEPROM READ WAVEFORMS
t RC ADDRESS
ADDRESS VALID
ECS1-2 t ACS OE t ACC EEPROM DATA OUTPUT
HIGH Z
t OE t DF
NOTES: OE may be delayed up to tACS - tOE after the falling edge of ECS without impact on tOE or by tACC - tOE after an address change without impact on tACC.
t OH
OUTPUT VALID
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
8
WSE128K16-XXX
EEPROM DATA POLLING
The WSE128K16-XXX offers a data polling feature for the EEPROM which allows a faster method of writing to the device. Figure 11 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on D7 (for each chip.) Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. EEPROM DATA POLLING CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Data Hold Time OE Hold Time OE To Output Valid Write Recovery Time Symbol tDH tOEH tOE tWR 0 Min 10 10 55 Max Unit ns ns ns ns
FIG. 10
EEPROM DATA POLLING WAVEFORMS
EWE1-2
ECS1-2 t OEH OE t DH t OE HIGH Z t WR ADDRESS
ED7
9
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSE128K16-XXX
EEPROM PAGE WRITE OPERATION
The WSE128K16-XXX has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150s or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the 150s time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. EEPROM PAGE WRITE CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Page Mode Write Characteristics Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Address Hold Time (1) Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High tWC tAS tAH tDS tDH tWP tBLC tWPH 50 0 100 100 10 150 150 Symbol Min Max 10 ms ns ns ns ns ns s ns Unit
1. Page address must remain valid for duration of write cycle.
FIG. 11
EEPROM PAGE MODE WRITE WAVEFORMS
OE
ECS1-2
t WP EWE1-2
t WPH
t BLC
t AS ADDRESS
VALID ADDRESS
t AH
t DS EEPROM DATA
t DH
BYTE 0 BYTE 1 BYTE 2 BYTE 3
t WC
BYTE 127
VALID DATA
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
10
WSE128K16-XXX
FIG. 12
EEPROM SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS
NOTES: 1. Data Format: ED7 - ED0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded.
(c) (c)
WRITES ENABLED(2)
(c)
(c)
ENTER DATA PROTECT STATE
11
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WSE128K16-XXX
EEPROM SOFTWARE DATA PROTECTION
A software write protection feature may be enabled or disabled by the user. When shipped by WEDC, the WSE128K16-XXX has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device, however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer.
FIG. 13
EEPROM SOFTWARE DATA PROTECTION DISABLE ALGORITHM(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS
(c) (c) (c) (c) (c)
EEPROM HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the WSE128K16-XXX. These are included to improve reliability during normal operation: a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5msec typical before allowing write cycles. b) VCC sense While below 3.8V typical write cycles are inhibited. c) Write inhibiting Holding OE low and either ECS or EWE high inhibits write cycles. d) Noise filter Pulses of <8ns (typ) on EWE or ECS will not initiate a write cycle.
(3)
EXIT DATA PROTECT STATE
NOTES: 1. Data Format: ED7 - ED0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
(c) (c) 12
WSE128K16-XXX
PACKAGE 400:
66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) 0.25 (0.010) SQ
PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171) MAX 3.81 (0.150) 0.13 (0.005) 2.54 (0.100) TYP 1.42 (0.056) 0.13 (0.005) 0.76 (0.030) 0.13 (0.005) 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
WSE128K16-XXX
PACKAGE 509:
68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) 0.26 (0.010) SQ 22.36 (0.880) 0.26 (0.010) SQ 4.57 (0.180) MAX 0.27 (0.011) 0.04 (0.002)
Pin 1
0.25 (0.010) REF
24.03 (0.946) 0.26 (0.010) 1 / 7 1.0 (0.040) 0.127 (0.005)
R 0.25 (0.010) 0.19 (0.007) 0.06 (0.002)
23.87 (0.940) REF
DETAIL A
1.27 (0.050) TYP 0.38 (0.015) 0.05 (0.002) 20.3 (0.800) REF SEE DETAIL "A"
The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form.
0.940" TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
14
WSE128K16-XXX
ORDERING INFORMATION W S E 128K16 - XXX X X X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial
-55C to +125C -40C to +85C 0C to +70C
PACKAGE TYPE: H1 = 1.075" sq. Ceramic Hex-In-line Package, HIP (Package 400) G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509) ACCESS TIME (ns) 35 = 35ns SRAM and 150ns EEPROM 42 = 45ns SRAM and 120ns EEPROM 73 = 70ns SRAM and 300ns EEPROM ORGANIZATION, 128K x 16 EEPROM SRAM WHITE ELECTRONIC DESIGNS CORP.
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com

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